1. Technical Field
The present invention relates generally to equalization techniques for high-speed data and more specifically to implementations of decision feedback equalizer circuits and methods for high-speed data communications with improved power efficiency.
2. Description of the Related Art
As the processing power of digital computing engines grows with improvements in technology, and increasingly interconnected networks are developed to harness this power, higher bandwidth data transmission is needed in systems such as servers and data communication routers. Increasing serial link data rates above a few gigabits per second becomes challenging, due to limited channel bandwidth. The bandwidth of an electrical channel (e.g., transmission line) may be reduced by several physical effects, including skin effect, dielectric loss, and reflections due to impedance discontinuities. In the time domain, limited channel bandwidth leads to broadening of the transmitted pulses over more than one unit interval (UI), and the received signal suffers from intersymbol interference (ISI).
An effective method of compensating for the signal distortions due to limited channel bandwidth is to add equalization functions to the input/output (I/O) circuitry. The use of a nonlinear equalizer known as a decision-feedback equalizer (DFE) in the receiver is particularly well-suited to equalizing a high-loss channel. Unlike linear equalizers, the DFE is able to flatten the channel response (and reduce signal distortion) without amplifying noise or crosstalk, which is a critical advantage when channel losses exceed 20-30 dB.
Referring to FIG. 1, a conventional multi-tap DFE 10 is illustrated. A binary output of a decision-making slicer (or latch) 12 is captured in a shift register delay line formed from a sequence of latches 14. Previously decided bits stored in the shift register (14) are fed back with weighted tap coefficients (H1, H2, . . . , HN) and added to the received input signal by means of a summing amplifier (or summer) 16. If the magnitudes and polarities of the tap weights (H1, H2, etc.) are properly adjusted to match the channel characteristics, the ISI from the previous bits in the data stream (termed “post-cursor ISI”) will be cancelled, and the bits can be detected by the slicer 12 with a low bit error rate (BER). The adjustment of the tap weights can be performed either manually or automatically by an appropriate adaptive algorithm.
In general, the larger the number of taps that can be applied toward canceling ISI, the more effective the equalization becomes. Practical DFE implementations often employ as many as 10 feedback taps in order to accomplish equalization of difficult electrical channels at multi-gigabit-per-second data rates. Unfortunately, the large number of latches and feedback circuits used in a multi-tap DFE consumes significant power and chip area. In some applications, such as a high-end processor chip having thousands of I/Os, the power and area costs of a conventional multi-tap DFE are prohibitive, as the I/O circuitry would consume most of the system power and area budgets.
The area and power requirements of I/O circuitry will become even more stringent with the introduction of dense, fine-pitch silicon packaging technologies, which are expected to be capable of supporting tens of thousands of high data rate I/Os for local chip-to-chip interconnect. One example of such a dense packaging technology is a silicon carrier, the basic concept of which is sketched in FIG. 2.
Referring to FIG. 2, two chips 20 and 22 are mounted to silicon carrier 24 and connected together with surface wiring 26. The pitch of this surface wiring 26, which is fabricated with standard CMOS back-end-of-line (BEOL) processing, is only a couple of microns and permits a dense array of silicon carrier links to be formed between the chips 20 and 22. Silicon through vias 28 are used to connect power and signals vertically between the chips 20 and 22 and conventional first-level packaging. Due to their fine dimensions, the surface wires 26 used to form the silicon carrier links exhibit significant resistance per unit length.